This application contains subject matter similar to subject matter disclosed in copending U.S. patent application Ser. No. 09/805,974, filed on Mar. 15, 2002.
1. Field of the Invention
The present invention relates to improved methods for performing plasma ashing of a photoresist material. More specifically, the present invention relates to improved methods for performing plasma ashing of patterned photoresist layers subsequent to formation of openings in a dielectric layer as part of multi- metallization level processing utilized in the fabrication of high integration density, semiconductor integrated circuit (IC) devices having submicron-dimensioned design features, wherein deleterious reaction of underlying metallization features with the gas(es) utilized for plasma ashing of photoresist is advantageously eliminated, or at least substantially reduced.
2. Background of the Invention
The escalating requirements for high integration density and performance associated with ultra large-scale (xe2x80x9cULSIxe2x80x9d) integration semiconductor device wiring and interconnection require responsive changes in interconnection technology. Such escalating requirements have been difficult to satisfy in terms of providing a low resistance-capacitance (xe2x80x9cRCxe2x80x9d) interconnection pattern, particularly wherein the various metallization features, e.g., vias, contacts, trenches, etc., are submicron-dimensioned and have high aspect ratios due to micro-miniaturization.
Conventional semiconductor IC devices typically comprise a semiconductor substrate, such as a monocrystalline silicon (Si) wafer including a plurality of active device regions formed thereon or therein, and a plurality of pairs of overlying, sequentially formed inter-layer dielectrics (xe2x80x9cILDxe2x80x9ds) and patterned metal layers. An integrated circuit is formed therefrom containing a plurality of electrically conductive patterns comprising conductive lines separated by interwiring spaces, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of different layers, i.e., upper and lower vertically spaced-apart layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes an electrical contact with an active device region on or in the semiconductor substrate, such as a source or drain region of a transistor. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor IC devices comprising five (5) or more such levels of vertically interconnected metallization are becoming more prevalent as device geometries decrease into the deep submicron range.
A conductive plug filling a via opening is typically formed by a process sequence comprising: (1) depositing an inter-layer dielectric (ILD) on a patterned, electrically conductive layer, e.g., a metal layer comprising at least one metal feature; (2) forming a desired opening in the ILD, as by conventional photolithographic masking and etching techniques, and filling the opening with an electrically conductive material, e.g., tungsten (W); and (3) removing excess conductive material deposited on the surface of the ILD during filling of the opening, as by chemical-mechanical polishing/planarization (xe2x80x9cCMPxe2x80x9d).
One such method for fabricating electrically conductive vias is termed xe2x80x9cdamascenexe2x80x9d type processing and basically involves the formation of an opening in an ILD which is filled with a metal plug. xe2x80x9cDual-damascenexe2x80x9d processing techniques involve formation of an opening in an ILD comprising a lower, contact or via opening section communicating with an upper, trench opening section, followed by filling of both the lower and upper sections of the opening with an electrically conductive material, typically a metal or metallic material, to simultaneously form a conductive (via) plug in electrical contact with a conductive line.
Referring now to FIGS. 1(A)-1(C), illustrated therein in schematic, cross-sectional form, are several stages of a typical photolithographic masking+ etching process conventionally utilized for forming an opening in an ILD layer for use as, for example, a via, bus line, bit line, word line, or interconnection line in metallization processing of semiconductor IC devices, e.g., according to the above-described damascene-type techniques.
Referring particularly to FIG. 1, precursor structure 1 is of conventional structure and includes a lower metal feature 11, e.g., of copper (Cu) or a Cu-based alloy, in-laid within a first, or lower, ILD layer 10 overlying a substrate (not shown in the figure for illustrative simplicity), typically a monocrystalline Si wafer. Precursor structure 1 further comprises a thin nitride layer 14, typically a silicon nitride (SixNy) layer from about 300-1000 xc3x85 thick, e.g., about 500 xc3x85 thick, formed, as by conventional techniques, to overlie the ILD layer 10 and its in-laid metal feature 11. Second, or upper ILD layer 12 is formed, as by conventional deposition techniques, to overlie the thin nitride layer 14. In this context, portion 14xe2x80x2 of thin nitride layer 14 overlying metal feature 11 serves both as an etch stop layer during patterning of the second, upper ILD layer 12 to form a desired opening 15 therein as part of the metallization process, and as a protective layer for preventing deleterious reaction of the metal feature 11, e.g., oxidation, nitridation, etc., during processing antecedent to filling the opening with a metal material, e.g., during reactive plasma etching of the second, upper ILD layer 12 to form opening 15. Organic-based photoresist layer 13 formed over the second, upper ILD layer 12 and patterned by conventional photolithographic masking and etching techniques serves as an etch mask during the reactive plasma etching.
Adverting to FIG. 1(B), subsequent to formation of opening 15 in second, upper ILD layer 12, according to conventional processing methodology, the patterned photoresist mask is then removed by means of a plasma ashing process, typically utilizing an oxygen (O2) or nitrogen (N2)-based plasma (or a mixed O2/N2 or N2/H2 plasma) with admixed argon (Ar) gas functioning as an inert carrier gas/diluent for the O2, N2, O2/N2, or N2/H2.
As utilized herein, the term xe2x80x9cplasma ashingxe2x80x9d designates plasma processes for removing organic-based photoresists, e.g., subsequent to their use as etch masks, etc. By way of illustration only, a typical O2-based plasma ashing reaction is conducted (in a suitable reactor) between a carbon (C)- and hydrogen (H)-containing photoresist material generally designated by the formula CxHy, and plasma-activated oxygen species, generally designated as O*. according to the following equation, in which each of the reaction products is volatile and thus readily removed from the reactor chamber:
CxHy+O*=CO(gas)+H2O(gas)+CO2(gas)
The plasma ashing process is conducted within the interior space of a suitably configured reactor with radio frequency (RF) or microwave (xcexcwave) energization at an applied power density determined in view of a number of process/apparatus parameters, including, inter alia, the reactor size, particular ashing gas or gases, their flow rate(s) and pressure(s), photoresist composition, desired ashing rate, substrate temperature, etc. As a consequence of the plurality of process variables/parameters, the power level applied to the reactor typically is optimized for use in a particular situation/application.
As indicated above, the active plasma ashing gases, e.g., O2, N2, O2/N2, or N2/H2 mixtures, are frequently supplied to the interior space of the plasma reactor admixed with inert argon (Ar) gas as a carrier gas/diluent, in order to facilitate plasma formation and moderate the plasma ashing reaction. However, as indicated in FIG. 1(B), argon ions (Ar+) generated in the ashing plasma bombard the exposed surfaces of the precursor structure 1 to sputter etch the exposed surfaces thereof at various etching rates, depending upon the particular material. However, inasmuch as the portion of the nitride etch stop/protective layer 14 exposed at the bottom of opening 15 is initially very thin, typically only about 500 xc3x85 thick, any loss of thickness thereof arising from sputter etching by Ar+ ions during plasma ashing of the photoresist layer 13 for removal thereof, is problematic from the viewpoint of the requirement for maintaining the integrity and continuity of the thin nitride layer 14 prior to its desired removal immediately before opening 15 is filled with a metal, as in via formation.
Referring now to FIG. 1(C) illustrating the state of precursor structure 1 after completion of plasma ashing processing for removal of the photoresist layer 13, it is evident that a significant fraction of the thickness of the thin nitride layer 14 has been removed during the course of the plasma ashing due to physical sputter etching by bombardment of the workpiece by Ar+ ions generated in the plasma, thereby reducing its integrity and protective (e.g., oxidation preventive) characteristics. Further, in some instances, for example as indicated in the figure by reference numeral 16, removal of the thin nitride layer 14 is sufficiently complete as to expose portions of the upper surface of the underlying metallization feature 11, and, in extreme instances, expose the entire upper surface thereof. As a consequence, at least portions of the upper surface of the metallization feature 11 are subject to deleterious reaction with the active plasma gases during the plasma ashing, such as O2, N2, O2/N2, or N2/H2 mixtures, whereby the upper surface of the metallization feature 11 is oxidized, nitrided, or oxynitrided to form a high resistance surface layer inimical to good electrical contact formation/adhesion with the metal material which subsequently fills the opening 15.
Accordingly, there exists a need for improved methodology for performing simple, reliable, rapid, and cost-effective plasma ashing processing of photoresists for removal thereof subsequent to their use as etch masks, which methodology effectively avoids the drawbacks and disadvantages associate with conventional techniques and provides, inter alia, no or at least a substantially reduced amount of disadvantageous, deleterious physical sputtering of the workpiece.
The present invention, wherein deleterious physical sputtering of a workpiece during removal of a photoresist therefrom by plasma ashing is eliminated, or at least substantially reduced, in which: (1) argon (Ar) gas as the inert carrier gas/diluent for the O2, N2, O2/N2, N2/H2 active plasma ashing gas or gases is replaced with an inert carrier gas/diluent having an atomic weight greater than that of Ar, such as krypton (Kr) and xenon (Xe); and (2) the electrical power supplied to the plasma reactor is less than that supplied to the plasma reactor when Ar is utilized, effectively addresses and solves the need for improved methodology for use in removal of photoresist materials by means of plasma ashing, particularly in the manufacture of multi-level metallization semiconductor integrated circuit devices. Further, the methodology provided by the present invention can be easily implemented in a cost-effective manner utilizing conventional plasma reactor apparatus. Finally, the methodology afforded by the instant invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components.
An advantage of the present invention is an improved method for removing photoresist layers from a workpiece surface by means of plasma ashing.
Another advantage of the present invention is an improved method for performing plasma ashing of photoresist layers on a workpiece surface which incurs no, or at least substantially reduced, damage to the workpiece arising from sputter etching by ionized species of the carrier/diluent gas for the active plasma ashing gas.
Still another advantage of the present invention is an improved method for performing plasma ashing of photoresist layers as part of a process sequence for forming openings in a dielectric layer as part of a process for fabricating a semiconductor device including in-laid metallization.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of removing a photoresist layer from a workpiece by means of plasma ashing, comprising the steps of:
(a) providing the interior space of a plasma reactor with a workpiece including at least one layer of a photoresist material on a surface thereof;
(b) supplying the interior space of the reactor with a gas mixture comprising a plasma ashing gas and a carrier gas/diluent for the plasma ashing gas, the carrier gas/diluent comprising an inert gas having an atomic weight greater than that of argon (Ar); and
(c) removing the at least one layer of photoresist material from the workpiece surface by generating a plasma comprising the plasma ashing gas and the carrier gas/diluent within the interior space of the reactor by supplying electrical power thereto at a level which is less than that supplied to the reactor when utilizing Ar gas as a carrier gas/diluent for the plasma ashing gas, whereby deleterious sputter etching of the workpiece resulting from bombardment of the workpiece by the ionized carrier gas/diluent of the plasma is eliminated, or at least substantially reduced, relative to when Ar gas is utilized as the carrier gas/diluent.
According to embodiments of the present invention, step (b) comprises supplying the interior space of the reactor with an oxygen/krypton (O2/Kr) gas mixture, an oxygen/xenon (O2/Xe) gas mixture, a nitrogen/krypton (N2/Kr) gas mixture, an oxygen/nitrogen/krypton (O2/N2/Kr) gas mixture, a nitrogen/hydrogen/krypton (N2/H2/Kr) gas mixture, a nitrogen/xenon (N2/Xe) gas mixture, an oxygen/nitrogen/xenon (O2/N2/Xe) gas mixture, or a nitrogen/hydrogen/xenon (N2/H2/Xe) gas mixture; and step (c) comprises supplying the interior space of the reactor with RF or microwave (xcexcwave) electrical power.
In accordance with embodiments of the present invention, step (a) comprises providing a workpiece including at least one opening extending through a dielectric layer overlying a semiconductor substrate, the opening including a bottom and formed by an etching process utilizing the at least one layer of photoresist material as an etch mask.
According to particular embodiments of the present invention, step (a) comprises providing a workpiece wherein the bottom of the at least one opening overlies at least a portion of a metal feature of the workpiece, with a thin layer of a protective material overlying at least the surface of the metal feature at the bottom of the opening; and step (c) comprises eliminating, or at least substantially reducing, sputter etching of the thin, protective layer at the bottom of the opening arising from bombardment by ions of the carrier/inert gas, thereby maintaining protection of the underlying metal feature from reaction with the plasma ashing gas during the plasma ashing of the photoresist layer.
According to alternate embodiments of the present invention, step (a) comprises providing a workpiece wherein the at least one opening in the dielectric layer comprises an opening for forming an in-laid metallization feature utilizing single- or dual-damascene processing.
In accordance with particular embodiments of the present invention, step (a) comprises providing a workpiece wherein the at least one metal feature comprises copper (Cu) or a Cu-based alloy and the thin layer of protective material comprises a nitride.
According to another aspect of the present invention, a method of manufacturing a semiconductor device comprises the sequential steps of:
(a) providing a workpiece comprising:
(i) a semiconductor substrate having a surface;
(ii) a first dielectric layer overlying the substrate surface,
(iii) at least one metal feature in-laid in the surface of the dielectric layer;
(iv) a thin, protective/etch stop layer overlying the at least one in-laid metal feature and the first dielectric layer; and
(v) a second dielectric layer overlying the thin, protective/etch stop layer;
(b) forming a layer of a photoresist material over the surface of the second dielectric layer;
(c) patterning the layer of photoresist material to define at least one opening therein at least partly overlying the at least one metal feature;
(d) forming an opening extending through the second dielectric layer to the thin, protective/etch stop layer by an etching process utilizing the patterned layer of photoresist material as an etch mask, the opening comprising a bottom surface formed by the thin, protective/etch stop layer; and
(e) removing the patterned layer of photoresist material from the surface of the second dielectric layer by a plasma ashing process, comprising:
(i) installing the etched workpiece within the interior space of a plasma reactor;
(ii) supplying the interior space of the reactor with a gas mixture comprising a plasma ashing gas and a carrier gas/diluent for the plasma ashing gas, the carrier gas/diluent comprising an inert gas having an atomic weight greater than that of argon (Ar); and
(iii) removing the patterned layer of photoresist material from the surface of the second dielectric layer by generating a plasma comprising the plasma ashing gas and the carrier gas/diluent within the interior space of the reactor by supplying electrical power thereto at a level less than that supplied to the reactor when utilizing Ar gas as a carrier gas/diluent for the plasma ashing gas, whereby deleterious sputter etching of the protective/etch stop layer forming the bottom surface of the opening in the second dielectric layer is eliminated, or at least substantially reduced, relative to when Ar gas is utilized as the carrier gas/diluent, thereby maintaining protection of the at least one in-laid metal feature from reaction with the plasma ashing gas during the plasma ashing of the patterned layer of photoresist material.
According to embodiments of the present invention, step (a) comprises providing a workpiece wherein the at least one in-laid metal feature comprises copper (Cu) or a Cu-based alloy and the thin, protective/etch stop layer comprises a nitride.
In accordance with embodiments of the present invention, step (e)(ii) comprises supplying said interior space of said reactor with an oxygen/krypton (O2/Kr) gas mixture, an oxygen/xenon (O2/Xe) gas mixture, a nitrogen/krypton (N2/Kr) gas mixture, an oxygen/nitrogen/krypton (O2/N2/Kr) gas mixture, a nitrogen/hydrogen/krypton (N2/H2/Kr) gas mixture, a nitrogen/xenon (N2/Xe) gas mixture, an oxygen/nitrogen/xenon (O2/N2/Xe) gas mixture, or a nitrogen/hydrogen/xenon (N2/H2/Xe) gas mixture; and step (e)(iii) comprises supplying said interior space of said reactor with RF or microwave (xcexcwave) electrical power.
According to particular embodiments of the present invention, step (d) comprises forming an opening extending through the second dielectric layer for forming an in-laid metallization feature utilizing single- or dual-damascene processing.
Additional advantages and aspects of the present invention will become apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.